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19-3398; Rev 0; 7/04
MAX1127 Evaluation Kit
General Description
The MAX1127 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1126/MAX1127 quad 12-bit analog-to-digital converter (ADC). The MAX1126/MAX1127 accept differential analog input signals. The EV kit generates these signals from user-provided single-ended input sources. The digital outputs produced by the ADC can be easily sampled with a user-provided, high-speed logic analyzer or data-acquisition system. The EV kit also features an on-board deserializer to ease integration with standard logic analysis systems. The EV kit operates from 1.8V and 3.3V power supplies (1.5V for the optional FPGA) and includes circuitry that generates a clock signal from an AC signal provided by the user. The EV kit comes with the MAX1127 installed. Order free samples of the pin-compatible MAX1126 to evaluate this part. Low-Voltage and Power Operation Optional On-Board Clock-Shaping Circuitry Serial SLVS/LVDS Outputs On-Board LVPECL Differential Output Drivers On-Board Deserializer LVDS Test Mode Assembled and Tested Also Evaluates the MAX1126
Features
Sample Rate Up to 65Msps (MAX1127)
Evaluates: MAX1126/MAX1127
Part Selection Table
PART MAX1126EGK MAX1127EGK SPEED (Msps) 40 65 PART MAX1127EVKIT
Ordering Information
TEMP RANGE 0C to +70C IC PACKAGE 68 QFN
Note: To evaluate the MAX1126, request a free MAX1126EGK sample with the MAX1127EVKIT.
Component Suppliers
SUPPLIER AVX Central Semiconductor Diodes Inc Panasonic TDK Vishay/Vitramon Zetex USA PHONE 843-946-0238 631-435-1110 805-446-4800 714-373-7366 847-803-6100 203-268-6261 631-543-7100 FAX 843-626-3123 631-435-1824 805-446-4850 714-737-7323 847-390-4405 203-452-5670 631-864-7630 WEBSITE www.avxcorp.com www.centralsemi.com www.diodes.com www.panasonic.com www.component.tdk.com www.vishay.com www.zetex.com
Note: Indicate that you are using the MAX1127 when contacting these component suppliers.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Component List
DESIGNATION C1-C12, C59-C64, C81-C85 C13-C20 C21-C28 QTY 23 0 8 DESCRIPTION 0.1F 20%, X5R 10V ceramic capacitors (0402) TDK C1005X5R1A104M Not installed (0603) 39pF 5%, 50V C0G ceramic capacitors (0402) TDK C1005C0G1H390J 1.0F 20%, X5R 6.3V ceramic capacitors (0402) TDK C1005X5R0J105M 220F 20%, 6.3V tantalum capacitors (C case) AVX TPSC227M006R0250 Not installed (C case) 10F 20%, X5R 10V ceramic capacitors (1210) TDK C3225X5R1A106M 2.2F 20%, X5R 6.3V ceramic capacitor (0603) TDK C1608X5R0J225M 0.01F 5%, 25V C0G ceramic capacitors (0603) TDK C1608C0G1E103J 0.1F 20%, X5R 6.3V ceramic capacitors (0201) TDK C0603X5R0J104M Dual Schottky diode (SOT23) Zetex BAS70-04 Central Semiconductor CMPD6263S Vishay BAS70-04 Diodes Inc BAS70-04 Green surface-mount LEDs (SS) Panasonic LNJ308G8LRA SMA PC-mount connectors Dual row, 40-pin headers U10 4 0 2-pin headers Not installed None None 1 16 1 DESIGNATION JU1-JU9, JU11, JU12, JU15- JU18 JU10 JU13 N1 QTY 15 0 1 1 DESCRIPTION Jumper, 3-pin headers Not installed (SIP-3) Jumper, dual row, 8-pin header Digital logic n-channel MOSFET (SOT23), top mark = 702 Central Semiconductor 2N7002
C29-C44, C77-C80, C92, C93 C45, C46, C47, C55, C86-C89 C48, C49, C50, C56 C51, C52, C53, C57, C90, C91
20
R1-R16, R22-R25, R82-R93 R17-R21, R58-R75 R26-R36, R76-R81 R37-R44 R45-R50 R51 R52, R53, R56 R54 R55 R57 R94, R95 R96, R97 R98 SW1 T1-T4 TP1-TP9 TP10-TP12 U1 U2 U3-U8
0
Not installed (0603)
8
23 0 8 6 1 3 1 1 1 2 2 1 1 4 9 0 1 1 6
49.9 1% resistors (0603) Not installed (0402) 10 1% resistors (0402) 100 1% resistors (0603) 100k potentiometer, 19 turn, 3/8in 4.02k 1% resistors (0603) 5k potentiometer, 19 turn, 3/8in 2k 1% resistor (0603) 13.0k 1% resistor (0603) 4.7k 5% resistors (0603) 330 5% resistors (1206) 10k 5% resistor (0603) Momentary pushbutton switch 1:1 800MHz RF transformers Mini-Circuits ADT1-1WT Test points (black) Not installed Maxim MAX1127EGK (68-pin QFN) Maxim MAX9111ESA (8-pin SO) Maxim MAX9375EUA (8-pin MAX) Xilinx XC2V80-5FG256C (FGBGA-256) or Xilinx XC2V80-5FG256I (FGBGA-256) Xilinx XC18V01SO20C (20-pin SO) Shunts MAX1127 PC board
0
6
C54
1
C58, C65-C76
13
C94-C121
28
D1
1
D2, D3 J1-J5 J6, J7, J12-J15 J8-J11 J16
2 5 6
U9
1
2
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MAX1127 Evaluation Kit
Quick Start
Recommended Equipment
* DC power supplies: Clock (CVDD) Analog (AVDD) Digital (OVDD) Buffers (VPECL) Optional Deserializer core (VD1.5) 1.5V, 200mA Deserializer I/O (VD3.3) 3.3V, 200mA * * * * * Signal generator with low-phase noise and low jitter for clock input signal (e.g., HP 8662A, HP 8644B) Four signal generators for analog signal inputs (e.g., HP 8662A, HP 8644B) Logic analyzer or data-acquisition system (e.g., HP 16500C, TLA621) Analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signal and clock signal Digital voltmeter 1.8V, 100mA 1.8V, 500mA 1.8V, 150mA 3.3V, 350mA 5) Connect the output of the analog bandpass filters to the SMA connectors labeled J1 to J4. The analog input signals may also be monitored at J8-J11. Note: All four channels may be operated independently or simultaneously. 6) Connect the logic analyzer to either header J6 (SLVS- or LVDS-compatible signals), or J12-J15 (deserialized 3.3V CMOS-compatible signals). See the Output Bit Locations section for header connections. 7) Connect a 1.8V, 500mA power supply to AVDD. Connect the ground terminal of this supply to GND. 8) Connect a 1.8V, 150mA power supply to OVDD. Connect the ground terminal of this supply to GND. 9) Connect a 1.8V, 100mA power supply to CVDD. Connect the ground terminal of this supply to GND. Note: When using the MAX9111, CVDD must be 3.3V 10) Connect a 3.3V, 350mA power supply to VPECL. Connect the ground terminal of this supply to GND. 11) Connect a 1.5V, 200mA power supply to VD1.5. Connect the ground terminal of this supply to GND. 12) Connect a 3.3V, 200mA power supply to VD3.3. Connect the ground terminal of this supply to GND. 13) Turn on all the power supplies. 14) Enable the signal generators. Set the clock signal generator to output a 48.75MHz to 65MHz signal, with an amplitude of 2.6VP-P or higher. Set the analog input signal generators to output the desired frequency with an amplitude 1VP-P. All signal generators should be phase locked. 15) Enable the logic analyzer. 16) Collect data using the logic analyzer.
Evaluates: MAX1126/MAX1127
Procedure
The MAX1127 EV kit is a fully assembled and tested surface-mount board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal generators until all connections are completed: 1) Verify that shunts are installed in the following locations: JU1-JU5 (1-2) All channels enabled JU6 (2-3) Single termination JU7 (2-3) LVDS outputs JU8 (2-3) Two's-complement output JU9 (2-3) Normal operation JU10, JU11, JU12 (2-3) 48.75MHz to 65MHz clock frequency range JU13 (3-4) Internal reference enabled JU15-JU18 (2-3) Deserializer outputs enabled 2) Connect the clock signal generator to the input of the clock bandpass filter. 3) Connect the output of the clock bandpass filter to the SMA connector labeled J5. 4) Connect the analog input signal generators to the inputs of the desired analog bandpass filters.
Detailed Description
The MAX1127 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1126 (40Msps) or MAX1127 (65Msps), 12-bit serial SLVS/LVDS output ADCs. The EV kit comes with the MAX1127, which can be evaluated with a maximum clock frequency (fCLK) of 65MHz. The MAX1127 accepts differential input signals; however, on-board transformers (T1-T4) convert a readily available single-ended source output to the required differential signal. The input signals of the MAX1127 can be measured using a differential oscilloscope probe at headers J8-J11.
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MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Output level translators (U3-U8) buffer and convert the SLVS/LVDS output signals of the MAX1127 to higher voltage LVPECL signals that can be captured by a wide variety of logic analyzers. The SLVS/LVDS outputs are accessible at header J6. The LVPECL outputs are accessible at header J7. The EV kit is designed as a four-layer PC board to optimize the performance of the MAX1127. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals; 50 coplanar transmission lines are used for analog and clock inputs and 100 differential coplanar transmission lines are used for all digital LVDS outputs. All differential outputs are properly terminated with 100 termination resistors between true and complementary digital outputs. The trace lengths of the 100 differential SLVS/LVDS lines are matched to within a few thousandths of an inch to minimize layout-dependent data skew. control the power-management features of the data converter. See Table 1 for shunt positions.
Clock
By default, the MAX1127 EV kit directly connects a user-provided AC-coupled clock signal to the MAX1127 clock input. In this mode, diode D1 limits the amplitude of the clock signal. Overdriving the clock input (J5) can increase the slew rate of the differential signal, thereby reducing clock jitter. The MAX1127 EV kit also features an optional on-board clock-shaping circuit that generates a clock signal with variable duty cycle from an AC-coupled sine-wave signal applied to the clock SMA connector (J5). To use this circuitry, cut the trace on the printed circuit (PC) board at R78 and install 0 resistors at R77 and R35. The frequency of the signal should not exceed 65MHz for the MAX1127. The sinusoidal input signal frequency (fCLK) determines the sampling rate of the ADC. Optional Clock-Shaping Circuit A differential line receiver (U2) processes the clockinput signal and generates the required CMOS clock signal. When using this circuitry, the voltage at the CVDD pad must be at least 3.3V The signal's duty cycle can be adjusted with potentiometer R54. With a 3.3V clock supply voltage (CVDD), a clock signal with a 50% duty cycle (recommended) can be achieved by adjusting R54 until a voltage of 1.32V is produced across test points TP6 and TP7. The clock signal can be observed at TP8. PLL Frequency-Mode Selection When driving the MAX1127 EV kit with anything other than the default 65MHz clock signal, the phased-
Power Supplies
For best performance, the MAX1127 EV kit requires separate analog, digital, clock, and buffer power supplies. Two 1.8V power supplies are used to power the analog and digital portion of the MAX1127. The clock circuitry is powered by a 1.8V power supply (if using the MAX9111, see the Optional Clock-Shaping Circuit section). A separate 3.3V power supply is used to power the output buffers (U3-U8) of the EV kit. MAX1127 Power-Down The MAX1127 features several power-management features. In addition to a global device power-down pin, the MAX1127 offers an independent power-down pin for each channel of the ADC. Jumpers JU1-JU5
Table 1. Power-Down Shunt Settings (JU1-JU5)
JUMPER JU1 (PD0) JU2 (PD1) JU3 (PD2) JU4 (PD3) SHUNT POSITION 1-2 2-3* 1-2 2-3* 1-2 2-3* 1-2 2-3* POWER-DOWN CONNECTIONS AVDD GND AVDD GND AVDD GND AVDD GND AVDD GND CHANNEL 0 1 2 3 ALL CHANNELS DESCRIPTION Channel 0 disabled Channel 0 enabled Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled All channels disabled All channels enabled
1-2 JU5 (PDALL) 2-3* *Default configuration: JU1-JU5 (2-3).
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MAX1127 Evaluation Kit
locked-loop (PLL) circuit of the MAX1127 must be set accordingly. Refer to the MAX1127 data sheet for further details about the operation of the internal PLL. Jumpers JU10, JU11, and JU12 control the PLL mode of the MAX1127. See Table 2 for shunt positions. Ensure that the desired clock frequency falls between the min/max limits in Table 2. data synchronization. Refer to the MAX1127 data sheet for more details. Output Format The digital output coding can be chosen to be either two's complement or straight offset binary by configuring jumper JU3. See Table 4 for jumper configuration.
Evaluates: MAX1126/MAX1127
Table 2. PLL Shunt Settings (JU10-JU12)
JUMPER JU11 2-3* SHUNT POSITION 2-3 1-2 1-2 JU12 2-3* 1-2 2-3 1-2 INPUT CLOCK RANGE (MHz) MIN 48.750 32.500 24.375 16.000 MAX 65.000 48.750 32.500 24.375
Table 4. Output Format Shunt Settings (JU8)
SHUNT POSITION 1-2* T/B PIN DESCRIPTION Straight offset binary selected. Digital output in straight offset binary format. Two's complement selected. Digital output in two's complement format.
AVDD
*Default configuration: JU10, JU11, JU12 (2-3).
2-3
GND
Input Signal
Although the MAX1127 accepts differential analog input signals, the EV kit only requires a single-ended analog input signal, with an amplitude of less than 1.4VP-P provided by the user. On-board transformers (T1-T4) convert the single-ended analog input signal and generate differential analog signals at the ADC's differential input pins.
*Default configuration: JU8 (1-2).
Reference Voltage
The MAX1127 EV kit can be configured to use the MAX1127's internal reference, or a stable, low-noise, external reference. Use jumper JU13 to configure the desired reference mode. See Table 3 for shunt settings.
Double-Termination Settings The MAX1127 features trimmed, internal 100 termination resistors between the positive (true) and negative (complementary) line of each output (D0-D3, CLK, and FRAME). Use jumper JU6 to switch the resistors into the circuit (double termination), or switch the resistors out of the circuit (single termination). See Table 5 for shunt positions.
Table 5. Double Termination Shunt Settings (JU6)
SHUNT POSITION 1-2 2-3* DT PIN AVDD GND DESCRIPTION Double termination selected. Outputs are double terminated. Single termination selected. Outputs are single terminated.
Table 3. Reference Shunt Settings (JU13)
SHUNT POSITION 1-2 3-4* 5-6 7-8 DESCRIPTION Internal reference disabled. Apply an external reference voltage at the REFIO pad. Internal reference enabled. RESERVED. DO NOT USE.
*Default configuration: JU6 (2-3).
*Default configuration: JU13 (3-4).
Output Signal
The MAX1127 features four, serial, LVDS-compatible, digital outputs. Each output transmits the converted analog input signals of channels 0 through 3. Two additional outputs (CLKOUT and FRAME) are provided for
SLVS Outputs The MAX1127 is capable of generating low-voltage differential signaling (LVDS) or scalable low-voltage signaling (SLVS) signals at its outputs. Jumper JU7 controls this feature of the MAX1127. See Table 6 for shunt positions. Regardless of which output signal type is selected, the output buffers (U3-U8) will convert the data to LVPECL logic levels.
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5
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Table 6. SLVS Shunt Settings (JU7)
SHUNT POSITION 1-2 2-3* SLVS/LVDS PIN AVDD GND DESCRIPTION SLVS outputs LVDS outputs
*Default configuration: JU7 (2-3).
LVDS Test Pattern To debug signal integrity problems, the MAX1127 can generate a factory-default test pattern on all the SLVS/LVDS output channels. Jumper JU9 controls this feature. See Table 7 for shunt positions.
Output Bit Locations The digital outputs of the MAX1127 are connected to a 40-pin header (J6). PC board trace length is matched to minimize data skew and improve the overall dynamic performance of the device. Additionally, six drivers (U3-U8) buffer and level translate the digital outputs to LVPECL-compatible signals. The drivers increase the differential voltage swing, and are able to drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to the 40-pin header (J7). See Table 8 for bit location of headers J6-J7.
On-Board Deserializer
The MAX1127 EV kit features an on-board deserializer that converts the serial outputs of the MAX1127 to a parallel data stream. The deserializer uses a delaylocked loop (DLL) to synchronize itself with the incoming serial data stream. After every change of the ADC clock frequency, reset the DLL by pressing SW1. If LED D3 is not lit, the serial data stream is not synchronized and the output of the deserializer is not valid.
Table 7. LVDS Test Pattern Shunt Settings (JU9)
SHUNT POSITION 1-2 2-3* LVDSTEST PIN AVDD GND DESCRIPTION Test pattern (0000 1011 1101) transmitted, LSB first, on all SLVS/LVDS outputs Normal operation
*Default configuration: JU9 (2-3).
Table 8. Output Bit Locations
SIGNAL CH0 CH1 CLKOUT FRAME CH2 CH3 P N P N P N P N P N P N UNBUFFERED (LVDS OR SLVS) J6-5 J6-6 J6-11 J6-12 J6-17 J6-18 J6-23 J6-24 J6-29 J6-30 J6-35 J6-36 BUFFERED (LVPECL) J7-5 J7-6 J7-11 J7-12 J7-17 J7-18 J7-23 J7-24 J7-29 J7-30 J7-35 J7-36 DESCRIPTION Channel 0 Channel 1 Clock Frame Channel 2 Channel 3
P: True N: Complementary
6
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MAX1127 Evaluation Kit
Channel 0 through channel 3 data is captured on headers J12 through J15. See Table 9 for bit locations. Deserializer Output Enables Jumpers JU15-JU18 control the respective CH0-CH3 output enables of the deserializer. See Table 10 for shunt positions.
Evaluates: MAX1126/MAX1127
Table 9. Output Bit Locations (J12-J15)
BIT CLK D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POSITION CH0 J12-38 J12-26 J12-24 J12-22 J12-20 J12-18 J12-16 J12-14 J12-12 J12-10 J12-8 J12-6 J12-4 CH1 J13-38 J13-26 J13-24 J13-22 J13-20 J13-18 J13-16 J13-14 J13-12 J13-10 J13-8 J13-6 J13-4 CH2 J14-38 J14-26 J14-24 J14-22 J14-20 J14-18 J14-16 J14-14 J14-12 J14-10 J14-8 J14-6 J14-4 CH3 J15-38 J15-26 J15-24 J15-22 J15-20 J15-18 J15-16 J15-14 J15-12 J15-10 J15-8 J15-6 J15-4
Evaluating the MAX1126
The MAX1127 EV kit can also be used to verify the MAX1126 performance. To evaluate the MAX1126, replace the MAX1127 with a free MAX1126EGK sample.
Table 10. Deserializer Output Enables (JU15-JU18)
SHUNT POSITION 1-2 2-3* DESCRIPTION Deserializer output disabled Deserializer output enabled
*Default configuration: JU15-JU18 (2-3).
Note: Odd-numbered pins are connected to ground. Remaining pins are No Connects.
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7
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
AVDD
AVDD CVDD OVDD
8 9 10 18 20 25 26 27 58 59 60 62 61 21 34 37 40 43 46 49 52 AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD CVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD AVDD 51 R45 100 1% OUTON C1 0.1F R17 49.9 1% R1 OPEN C13 SHORT R37 10 1% R26 SHORT C21 39pF OUT1N C5 0.1F J8 R27 SHORT C22 39pF CLKOUTP 3 IN0N CLKOUTN FRAMEP 5 IN1P FRAMEN J9 R12 OPEN C6 0.1F OUT2P R29 SHORT C24 39pF 41 39 R49 100 1% OUT2N OUT3P 12 IN2P OUT3N J10 R14 OPEN C7 0.1F R31 SHORT C26 39pF PD2 R32 SHORT C27 39pF J11 PD0 R33 SHORT C28 39pF 16 TP9 19 IN3N I.C. PDALL 57 32 JU5 AVDD PLL3 33 32 JU12 DT PLL2 29 1 2 JU7 AVDD 1 2 JU8 AVDD 1 2 JU9 CLK REFIO 23 66 C9 0.1F GND GND GND GND GND GND GND GND GND GND INTREF 67 R57 13.0k 1% 2 3 R51 100k 1 TP5 3 64 LVDSTEST PLL0 30 TP8 3 63 T/B 3 SLVS/LVDS PLL1 31 32 JU10 1 SHORT PINS 2 AND 3 (PC TRACE) R36 SHORT JU13-5JU13-6 JU13-7JU13-8 AVDD 32 32 JU11 AVDD 1 REFADJ JU13 JU13-1JU13-2 REFADJ JU13-3JU13-4 AVDD 1 REF 1 PD3 13 IN2N 55 32 JU3 15 IN3P AVDD PD1 54 32 JU2 AVDD 53 32 JU1 AVDD 1 C8 0.1F 1 1 56 32 JU4 AVDD GND 5 R78 SHORT 1 35 38 36 R50 100 1% D3N AVDD R35 OPEN 6 D2N D3P 3 C58 0.01F 8 7 OUT VCC U2 N.C. IN1N N.C. IN1P N.C. 1 3 2 4 C11 0.1F C10 0.1F TP6 R52 4.02k 1% R54 5k TP7 3 R55 2k 1% R77 OPEN 44 42 R48 100 1% FMN D2P OUT1P 2 IN0P 47 45 R47 100 1% CKN FMP VPECL 50 48 R46 100 1% O1N CKP AVDD AVDD C45 220F 6.3V C48 OPEN C51 10F C77 1.0F CVDD CVDD C47 220F 6.3V C49 OPEN C52 10F C78 1.0F DON O1P OVDD C37 1.0F C38 1.0F C39 1.0F C40 1.0F C41 1.0F C42 1.0F C43 1.0F CVDD C44 1.0F C29 1.0F C30 1.0F C31 1.0F C32 1.0F C33 1.0F C34 1.0F C35 1.0F C36 1.0F
OUT0P
DOP
J1
1 5 3
6 2 4 T1 R2 OPEN
R9 OPEN
TP1
R22 SHORT
R10 OPEN
GND
GND
C14 SHORT C15 SHORT
R38 10 1% R39 10 1%
VPECL C55 220F 6.3V C56 OPEN C57 10F C79 1.0F
OVDD
OVDD C46 220F 6.3V C50 OPEN C53 10F C80 1.0F
J2
C2 0.1F R18 49.9 1%
R3 OPEN
R28 SHORT C23 39pF
GND
GND
1 5 3
6 2 4 T2 R4 OPEN
R11 OPEN
TP2
R23 SHORT
U1
6 IN1N
CVDD
C54 2.2F
C16 SHORT C17 SHORT
R40 10 1% R41 10 1%
MAX1127
CVDD 2 R
D1 1 L CVDD
J3
C3 0.1F R19 49.9 1%
R5 OPEN
R30 SHORT C25 39pF
1 5 3
6 2 4 T3 R6 OPEN
R13 OPEN
1 2
TP3
CVDD R56 4.02k 1% R53 4.02k 1%
R24 SHORT
MAX9111
C12 0.1F R21 49.9 1%
J5
C18 SHORT C19 SHORT
R42 10 1% R43 10 1%
J4
C4 0.1F R20 49.9 1%
R7 OPEN
1 5 3
6 2 4 T4 R8 OPEN
R15 OPEN
TP4
R25 SHORT
R16 OPEN
C20 SHORT
R44 10 1%
AVDD 1 2 JU6 AVDD 3
28
1 4 7 11 14 17 22 24
65 R34 SHORT
68 R76 SHORT
Figure 1. MAX1127 EV Kit Schematic (Sheet 1 of 4) 8 _______________________________________________________________________________________
VPECL C59 0.1F
VPECL C60 0.1F
VPECL C61 0.1F
1 VCC OUT 7 IN OUT OUT IN R58 49.9 1% DIP 2 7 R61 49.9 1% 7 R64 49.9 1% 2 VCC D2P VCC VCC VCC
8 1 1
C65 0.01F BD0P 8 8 BD1P BD2P
C67 0.01F
C69 0.01F
DOP
VCC
2
IN
U3
DIN 3 IN GND BD0N 4 BD1N 5 4 5 GND GND GND BD2N OUT 6 IN OUT 6 3
U4 MAX9375
R62 49.9 1% R63 49.9 1% C68 0.01F D2N R66 49.9 1% R65 49.9 1%
U5 MAX9375
DON OUT 6 GND 5
MAX9375
R59 49.9 1% R60 49.9 1% C66 0.01F
3
IN
C70 0.01F
GND
4
Figure 1. MAX1127 EV Kit Schematic (Sheet 2 of 4)
VPECL C62 0.1F VPECL C63 0.1F VPECL C64 0.1F 8 1 CKP 2 IN OUT 7 R70 49.9 1% FMN IN 2 VCC FMP VCC 1 VCC VCC OUT 7 R67 49.9 1% C71 0.01F BD3P 8 BCKP C73 0.01F 8 VCC OUT 7 C75 0.01F BFMP
1
D3P
VCC
2
IN
U6
CKN 3 IN GND BD3N 4 BCKN 5 GND OUT 6
U7 MAX9375
R71 49.9 1% R72 49.9 1% C74 0.01F
U8 MAX9375
3 IN GND 4 GND 5 OUT 6
R73 49.9 1%
D3N OUT 6 GND 5
MAX9375
R68 49.9 1% R69 49.9 1% C72 0.01F
3
IN
R74 49.9 1%
R75 49.9 1%
C76 0.01F
GND
4
BFMN
J6
J7
DOP
J6-1 J6-3 J6-5 DON BDOP
J6-2 J6-4 J6-6
J7-1 J7-3 J7-5
J7-2 J7-4 J7-6
BDON
D1P
D1N BD1P
BD1N
CKP
CKN
BCKP
BCKN
FMP
FMN
BFMP
BFMN
D2P
D2N
BD2P
BD2N
D3P J6-37 J6-39 J6-38 J6-40
J6-7 J6-9 J6-11 J6-13 J6-15 J6-17 J6-19 J6-21 J6-23 J6-25 J6-27 J6-29 J6-31 J6-33 J6-35 D3N BD3P
J6-8 J6-10 J6-12 J6-14 J6-16 J6-18 J6-20 J6-22 J6-24 J6-26 J6-28 J6-30 J6-32 J6-34 J6-36
J7-7 J7-9 J7-11 J7-13 J7-15 J7-17 J7-19 J7-21 J7-23 J7-25 J7-27 J7-29 J7-31 J7-33 J7-35 J7-37 J7-39
J7-8 J7-10 J7-12 J7-14 J7-16 J7-18 J7-20 J7-22 J7-24 J7-26 J7-28 J7-30 J7-32 J7-34 J7-36 J7-38 J7-40
Evaluates: MAX1126/MAX1127
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BD3N
MAX1127 Evaluation Kit
9
Evaluates: MAX1126/MAX1127
MAX1127 Evaluation Kit
Figure 1. MAX1127 EV Kit Schematic (Sheet 3 of 4)
VD3.3 1 JU15 2 3 J13 J15 U9-D H1 H2 H3 J4 K4 L4 L13 K13 J13 H14 H15 H16 D7 E6 E7 G4 L96P_7 L96N_7 L94P_7 L94P_6 L91P_6 LO6P_6 LO6P_3 L91P_3 L94P_3 L94P_2 L96N_2 L96P_2 N.C. N.C. N.C. L91N_7 CLKDES XC2V80-5FG256C H4 L94N_7 P8 L95N_5/GCLK5S P5 LO3N_5/D4/AVP5 P4 LO2P_5/D7 N14 LO2P_3/VRN_3 N3 LO2P_6/VRN_6 M14 LO3N_3/VREF_3 M3 LO3N_6/VREF_6 K14 L91N_3 K3 L91N_6 J15 L96P_3 J14 L94N_3 G5 N.C. F5 N.C. F2 N.C. F1 N.C. J1 K2 L3 M4 N5 N8 N9 N12 M13 L14 K15 J16 C6 C7 D6 G3 CLKDES XC2V80-5FG256C U9-C D5 L96N_6 LO2N_0 P9 L93P_6 L95P_4/GCLK2P H13 LO6N_6 L94N_2 E15 LO3P_8 LO4N_2 G15 LO3_5/D5/AVN5 L93N_2 G14 L95P_5/GLCK4P L91P_2 G13 L95N_4/GCLK3S L91N_2 G1 LO3N_4/D2/AVP4 L93P_7/VREF_7 F14 LO3P_3 LO6P_2 F13 LO6N_3 LO6N_2 N7 L93P_3 N.C. N10 L96N_3 N.C. K5 N.C. N.C. L5 N.C. N.C. L2 N.C. N.C. L1 L91P_7 N.C. J15-1 J15-3 J15-5 J15-7 J15-9 J15-11 J15-13 J15-15 J15-17 J15-19 J15-21 J15-23 J15-25 J15-27 J15-29 J15-31 J15-33 J15-35 J15-37 J15-39 J15-2 J15-4 J15-6 J15-8 J15-10 J15-12 J15-14 J15-16 J15-18 J15-20 J15-22 J15-24 J15-26 J15-28 J15-30 J15-32 J15-34 J15-36 J15-38 J15-40 U9-A D3 LO4N_6 LO2N_7/VRP_ J2 LO1N_6 L96P_ J3 LO1P_6 L94N_ C12 LO1P_5/CS LO2N_ C9 LO1N_5/RDWR L95N_1/GCLK1P C8 L94N_5 L95P_0/GCLK6S P12 L96N_5/GCLK7S LO3P_4/D3/AVN4 C5 L96P_4/GCLKOP LO2P_0 B6 L94P_4 N.C. A6 LO1P_3 N.C. B11 LO1N_3 N.C. A11 LO4N_3 N.C. G12 N.C. N.C. F12 N.C. N.C. F15 N.C. N.C. F16 L93P_2/VREF_2 N.C. K1 M2 N2 R4 R7 R8 R9 R10 R13 N15 M15 K16 D10 E10 E11 G2 CLKDES XC2V80-5FG256C CLKDES XC2V80-5FG256C J13-1 J13-3 J13-5 J13-7 J13-9 J13-11 J13-13 J13-15 J13-17 J13-19 J13-21 J13-23 J13-25 J13-27 J13-29 J13-31 J13-33 J13-35 J13-37 J13-39 J13-2 J13-4 J13-6 J13-8 J13-10 J13-12 J13-14 J13-16 J13-18 J13-20 J13-22 J13-24 J13-26 J13-28 J13-30 J13-32 J13-34 J13-36 J13-38 J13-40 J14-1 J14-3 J14-5 J14-7 J14-9 J14-11 J14-13 J14-15 J14-17 J14-19 J14-21 J14-23 J14-25 J14-27 J14-29 J14-31 J14-33 J14-35 J14-37 J14-39 J14-2 J14-4 J14-6 J14-8 J14-10 J14-12 J14-14 J14-16 J14-18 J14-20 J14-22 J14-24 J14-26 J14-28 J14-30 J14-32 J14-34 J14-36 J14-38 J14-40 U9-B D2 L93N_6/VREF_6 LO2P_7/VRN_7 E14 L04P_6 LO3P_2/VREF_2 E13 LO2N_6/VRP_6 LO3N_2 P7 LO2N_5/D6 N.C. P10 L94_5/VREF_5 N.C. T5 L96P_5/GCLK6P N.C. T12 L96N_4/GCLK1S N.C. D15 L94N_4/VREF_4 LO2P_2/VRN_2 D14 LO2P_4/D1 LO2N_2/VRP_2 D12 LO2N_3/VRP_3 LO2P_1 D9 LO4P_3 L95P_1/GCLK0S D8 L93N_3/VREF_3 L95N_O/GCLK7P K12 N.C. N.C. L12 N.C. N.C. L15 N.C. N.C. L16 L93N_7 N.C. J14 3 3 3 JU16 2 JU17 2 JU18 2 1 1 1 VD3.3 VD3.3 VD3.3 R84 SHORT U9-H B4 LO1P_0 R82 SHORT BD3P LO1N_7 C1 BD3N R83 SHORT R85 SHORT R86 SHORT R87 SHORT B8 L96N_0/GLCK5P P11 N.C. R5 R88 SHORT B9 L96P_1/GLCK2S N.C. R89 SHORT A9 B10 A10 B12 A12 C13 LO1P_1 D16 BD0P R92 SHORT C16 BD0N L96N_1/GCLK3P L94P_1/VREF_1 L94N_1 LO3P_1/VRN_1 LO3N_1/VRP_1 R93 SHORT N.C. N.C. N.C. N.C. N.C. LO1N_2 P6 N11 N6 M11 M6 C4 A5 B5 A7 B7 A8 LO1P_7 LO1N_0 N.C. LO3P_0/VRN_0 N.C. LO3N_0/VRP_0 N.C. L94P_0 N.C. L94N_0/VREF_0 L96_0/GLCK4S N.C. D1 T11 T6 R12 R11 R6 R90 SHORT R91 SHORT B13 LO1N_1 XC2V80-5FG256C LO1P_2
10
J12
J12-1 J12-3 J12-5 J12-7 J12-9 J12-11 J12-13 J12-15 J12-17 J12-19 J12-21 J12-23 J12-25 J12-27 J12-29 J12-31 J12-33 J12-35 J12-37 J12-39
J12-2 J12-4 J12-6 J12-8 J12-10 J12-12 J12-14 J12-16 J12-18 J12-20 J12-22 J12-24 J12-26 J12-28 J12-30 J12-32 J12-34 J12-36 J12-38 J12-40
M1 N1 P1 T3 T4 T7 T8 T9 T10 P16 N16 M16 C10 C11 D11 G16
BD2P
BD2N
BFMP
BFMN
BCKP
BCKN
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BD1P
BD1N
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
VD3.3
VD3.3
18 VCC TDI TMS TCK 4 5 6 TDI TMS TCK
20 VCC
19 VCCO D0 D1 D2 D3 D4/CF 1 16 2 15 7 VD3.3 JU16-4 12 3 10 13 8 17 JU16-8 TDI-FPGA JU16-9 TMS CCLK D2 DONE R96 330 VD3.3 JU16-5 R95 4.7k INIT JU16-6 JU16-7 TDO TDI TCK R94 4.7k PROGRAM JU16-3 VD3.3 DIN VD3.3 JU16 JU16-1 JU16-2
U10 14 D5 XC18V01S020
D6 D7 CLK CE CEO OE/RESET TDO GND 11 9
VD3.3
VD1.5
VD3.3
T16 T1 R15 R2 P14 P3 L11 L6 K10 K9 K8 K7 J10 J9 J8 J7
U9-E XC2V80-5FG256C
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A1 A16 B2 B15 C3 C14 F6 F11 G7 G8 G9 G10 H7 H8 H9 H10
F8 F7 E8 F10 F9 E9 H12 H11 G11 J11 J12 K11 M9 L10 L9 M8
U9-F XC2V80-5FG256C
VCC0_0 VCC0_0 VCC0_0 VCC0_1 VCC0_1 VCC0_1 VCC0_2 VCC0_2 VCC0_2 VCC0_3 VCC0_3 VCC0_3 VCC0_4 VCC0_4 VCC0_4 VCC0_5 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
D4 D13 E5 E12 M5 M12 N4 N13 VD3.3
DIN TCK DONE PROGRAM CCLK TMS TDO TDI-FPGA INIT
P13 A15 R14 A2 P15 B14 C15 C2 T13
U9-G XC2V80-5FG256C
LO2N_4/DO/DIN VCCAUX TCK DONE PROG CCLK TMS TDO TDI LO1P_4/INIT VCCAUX VCCAUX VCCAUX LO4P_2 LO6N_7
R16 R1 B16 B1 E16 F4 1 TP12 VD3.3 TP11 TP10 SW1 D3 3 N1 2 R97 330
LO6P_7 F3 LO3N_7 E4
VCCO_7 G6 VCCO_7 VCCO_7 VCCO_6 VCCO_6 VCCO_6 VCCO_5 VCCO_5 H6 H5 J5 J6 K6 L7 L8 R81 SHORT
T14 LO1N_4/BY/ DOUT A3 RSVD A4 A13 T2 P2 R3 R80 SHORT R79 SHORT RSVD RSVD W0 W1 W2
LO3P_7/ E3 VREF_7 E2 LO4N_7 LO4P_7 N.C. N.C. PWRDOWN HSWAP_EN VBATT E1 M10 M7 T15 B3 A14
R98 10k
VD3.3
VD3.3 C86 220F 6.3V C87 220F 6.3V C90 10F C92 1.0F
VD3.3 C118 0.1F C119 0.1F C120 0.1F C121 0.1F
VD1.5 C110 0.1F C111 0.1F C112 0.1F C113 0.1F C114 0.1F C115 0.1F C116 0.1F C117 0.1F
VD3.3 C81 0.1F C82 0.1F C83 0.1F C84 0.1F C85 0.1F
GND
VD1.5
VD1.5 C88 220F 6.3V C89 220F 6.3V C91 10F C93 1.0F
VD3.3 C94 0.1F C95 0.1F C96 0.1F C97 0.1F C98 0.1F C99 0.1F C100 0.1F C101 0.1F C102 0.1F C103 0.1F C104 0.1F C105 0.1F C106 0.1F C107 0.1F C108 0.1F C109 0.1F
GND
Figure 1. MAX1127 EV Kit Schematic (Sheet 4 of 4) ______________________________________________________________________________________ 11
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Figure 2. MAX1127 EV Kit Component Placement Guide--Component Side
Figure 3. MAX1127 EV Kit PC Board Layout--Component Side
12
______________________________________________________________________________________
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Figure 4. MAX1127 EV Kit PC Board Layout (Inner Layer 2)--Ground Planes
Figure 5. MAX1127 EV Kit PC Board Layout (Inner Layer 3)--Power Planes
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13
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Figure 6. MAX1127 EV Kit PC Board Layout (Inner Layer 4)--Signal Layer
Figure 7. MAX1127 EV Kit PC Board Layout (Inner Layer 5)--Signal Layer
14
______________________________________________________________________________________
MAX1127 Evaluation Kit Evaluates: MAX1126/MAX1127
Figure 8. MAX1127 EV Kit PC Board Layout--Solder Side
Figure 9. MAX1127 EV Kit Component Placement Guide--Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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